Dual OV5640 Cameras

Installation of Dual OV5640 Module

Insert the module onto the development board as follows, ensuring the arrows are aligned. Additionally, jumper P2 to the +3.3V position to ensure the module is powered by 3.3V.

Create a New Vivado Project

The goal we want to achieve is to display the dual camera feed in real-time on both HDMI and LCD. The implementation approach is to use 2 write-only VDMA modules to transfer camera data to DDR, then use two read-only VDMA modules to retrieve data from DDR and display it on HDMI and LCD respectively through the v_axi4s_vid_out_0 IP core and v_axi4s_vid_out_1 IP core. Since this test involves both HDMI and LCD, we need to reference some engineering code from previous HDMI and LVGL tests.

Modify based on the previous HDMI project: First, enable two EMIO pins to connect to the camera's SCCB interface, and configure the pin constraints as follows:

#cam_scl:
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[9]}]
#cam_sda:
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[10]}]
#pull up
set_property PULLUP true [get_ports {emio_sccb_tri_io[9]}]
set_property PULLUP true [get_ports {emio_sccb_tri_io[10]}]

Modify the three FCLK clocks of the Zynq IP core to 100, 125, and 200. Among them, FCLK_CLK2 serves as the clock for the extended ENET1.

Search for vdma to add:

Configure the four vdma modules: two for reading and two for writing, and set the parameters according to the figures below.

Two read-only VDMA:

Two write-only VDMA configuration:

Add two clk_wiz IP cores, one to drive the HDMI display clock and one to drive the LCD display clock. Search for clk:

Set up the HDMI clk_wiz IP: Set it as a dynamic clock controlled by the AXI bus, with the input provided by FCLK_CLK0 at 100MHz:

HDMI requires two clocks, which have a 5x relationship:

Set up the LCD clk_wiz IP: Set it as a dynamic clock controlled by the AXI bus, with the input provided by FCLK_CLK0 at 100MHz:

LCD only needs one clock output enabled:

Refer to the previous HDMI Test document to add other required IP cores for HDMI display:

Add and search for the timing core, and configure it as shown below:

Search for the video out core and configure it as shown below:

A custom IP is required: dvi_transmitter. This IP core is located in the ip_repo folder of the project directory. We need to add it to the project's IP library. In the Block Design, connect the interface signals of the DVI Transmitter module and bring out the external ports (only the TMDS ports need to be brought out). The specific connection method is shown in the following figures:

Following the same steps as above, find our custom IP core ov5640_capture and add it to the project's IP library.

Search for v_vid_in_axi4s. The function of this module is to convert standard video format output into AXI4-Stream data flow. Configure it:

Connect ov5640, v_vid_in_axi4s, and the read-operation vdma as shown below:

Refer to the LVGL Test document to add a video out module. This module converts AXI4-Stream data flow into standard video format output, corresponding to the RGB LCD screen.

Add a Video Timing Controller module: Search for and add the video timing controller module, double-click to open the configuration page and configure it:

Add a constant module to add a constant value of 1, used to connect the ce and aclken enable signals of our various modules.

For subsequent connections, refer to the LVGL Test document. At this point, click Run Connection Automation to automatically connect the remaining wiring. After checking all items in the pop-up settings dialog, the system will automatically connect the remaining signal lines and add the required modules. The final generated overall block diagram is as follows:

Save the project, then click Source → Design Sources, right-click on the BLOCK project we created, and click Create HDL Wrapper to package the BLOCK file. At this point, the Block Design part is set up.

Configure the pins according to the schematic diagram: Configured .xdc:

​x
#----------------------Clock for the camera interface---------------------------
#72M
create_clock -period 13.888 -name camera_pclk [get_ports camera_pclk_0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets camera_pclk_0_IBUF]

create_clock -period 13.888 -name camera_pclk [get_ports camera_pclk_1]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets camera_pclk_1_IBUF]



#----------------------Camera interface 1---------------------------
set_property -dict {PACKAGE_PIN U14  IOSTANDARD LVCMOS33} [get_ports camera_rstn_0]
set_property -dict {PACKAGE_PIN U15  IOSTANDARD LVCMOS33} [get_ports camera_pwdn_0]
set_property -dict {PACKAGE_PIN U10  IOSTANDARD LVCMOS33} [get_ports {camera_data_0[0]}]
set_property -dict {PACKAGE_PIN Y11  IOSTANDARD LVCMOS33} [get_ports {camera_data_0[1]}]
set_property -dict {PACKAGE_PIN W11  IOSTANDARD LVCMOS33} [get_ports {camera_data_0[2]}]
set_property -dict {PACKAGE_PIN U7   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[3]}]
set_property -dict {PACKAGE_PIN V7   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[4]}]
set_property -dict {PACKAGE_PIN W6   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[5]}]
set_property -dict {PACKAGE_PIN V6   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[6]}]
set_property -dict {PACKAGE_PIN U5   IOSTANDARD LVCMOS33} [get_ports {camera_data_0[7]}]
set_property -dict {PACKAGE_PIN W13  IOSTANDARD LVCMOS33} [get_ports camera_href_0]
set_property -dict {PACKAGE_PIN T9   IOSTANDARD LVCMOS33} [get_ports camera_pclk_0]
set_property -dict {PACKAGE_PIN V12  IOSTANDARD LVCMOS33} [get_ports camera_vsync_0]
#cam_scl:
set_property -dict {PACKAGE_PIN T11  IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[7]}]
#cam_sda:
set_property -dict {PACKAGE_PIN T10  IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[8]}]
#pull up
set_property PULLUP true [get_ports {GPIO_0_0_tri_io[7]}]
set_property PULLUP true [get_ports {GPIO_0_0_tri_io[8]}]


#----------------------Camera interface 2---------------------------
set_property -dict {PACKAGE_PIN Y6  IOSTANDARD LVCMOS33} [get_ports camera_rstn_1]
set_property -dict {PACKAGE_PIN Y8  IOSTANDARD LVCMOS33} [get_ports camera_pwdn_1]
set_property -dict {PACKAGE_PIN T5  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[0]}]
set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {camera_data_1[1]}]
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {camera_data_1[2]}]
set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports {camera_data_1[3]}]
set_property -dict {PACKAGE_PIN W9  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[4]}]
set_property -dict {PACKAGE_PIN U9  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[5]}]
set_property -dict {PACKAGE_PIN U8  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[6]}]
set_property -dict {PACKAGE_PIN W8  IOSTANDARD LVCMOS33} [get_ports {camera_data_1[7]}]
set_property -dict {PACKAGE_PIN V8  IOSTANDARD LVCMOS33} [get_ports camera_href_1]
set_property -dict {PACKAGE_PIN Y7  IOSTANDARD LVCMOS33} [get_ports camera_pclk_1]
set_property -dict {PACKAGE_PIN Y9  IOSTANDARD LVCMOS33} [get_ports camera_vsync_1]
#cam_scl:
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[9]}]
#cam_sda:
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports {GPIO_0_0_tri_io[10]}]
#pull up
set_property PULLUP true [get_ports {emio_sccb_tri_io[9]}]
set_property PULLUP true [get_ports {emio_sccb_tri_io[10]}]

# beep
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[11]}]
set_property PACKAGE_PIN K18 [get_ports {GPIO_0_0_tri_io[11]}]

# PL_KEY0
set_property PACKAGE_PIN M14 [get_ports {GPIO_0_0_tri_io[0]}]
# PL_KEY1
set_property PACKAGE_PIN M15 [get_ports {GPIO_0_0_tri_io[1]}]
# PL_LED0
set_property PACKAGE_PIN N15 [get_ports {GPIO_0_0_tri_io[2]}]
# PL_LED1
set_property PACKAGE_PIN N16 [get_ports {GPIO_0_0_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[0]}]



set_property PACKAGE_PIN G14 [get_ports CAN_0_0_rx]
set_property PACKAGE_PIN J15 [get_ports CAN_0_0_tx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_0_rx]
set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_0_tx]



#set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0]
set_property PACKAGE_PIN M19 [get_ports {TMDS_0_tmds_data_p[2]}]
set_property PACKAGE_PIN G19 [get_ports {TMDS_0_tmds_data_p[1]}]
set_property PACKAGE_PIN J20 [get_ports {TMDS_0_tmds_data_p[0]}]
set_property PACKAGE_PIN L16 [get_ports TMDS_0_tmds_clk_p]
#set_property PACKAGE_PIN F16 [get_ports reset_rtl_0]


set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN L14 [get_ports IIC_0_0_sda_io]
set_property PACKAGE_PIN L15 [get_ports IIC_0_0_scl_io]

set_property PACKAGE_PIN F19 [get_ports MDIO_PHY_0_mdc]
set_property PACKAGE_PIN F20 [get_ports MDIO_PHY_0_mdio_io]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_0_mdc]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_PHY_0_mdio_io]
set_property PACKAGE_PIN E18 [get_ports {RGMII_0_rd[0]}]
set_property PACKAGE_PIN E19 [get_ports {RGMII_0_rd[1]}]
set_property PACKAGE_PIN D18 [get_ports {RGMII_0_rd[2]}]
set_property PACKAGE_PIN E17 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_tx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_txc]
set_property PACKAGE_PIN A20 [get_ports {RGMII_0_td[0]}]
set_property PACKAGE_PIN B20 [get_ports {RGMII_0_td[1]}]
set_property PACKAGE_PIN C20 [get_ports {RGMII_0_td[2]}]
set_property PACKAGE_PIN D19 [get_ports {RGMII_0_td[3]}]
set_property PACKAGE_PIN H17 [get_ports RGMII_0_rx_ctl]
set_property PACKAGE_PIN H16 [get_ports RGMII_0_rxc]
set_property PACKAGE_PIN D20 [get_ports RGMII_0_tx_ctl]
set_property PACKAGE_PIN B19 [get_ports RGMII_0_txc]

set_property SLEW FAST [get_ports {RGMII_0_td[0]}]
set_property SLEW FAST [get_ports {RGMII_0_td[1]}]
set_property SLEW FAST [get_ports {RGMII_0_td[2]}]
set_property SLEW FAST [get_ports {RGMII_0_td[3]}]
set_property SLEW FAST [get_ports RGMII_0_tx_ctl]
set_property SLEW FAST [get_ports RGMII_0_txc]

create_clock -period 8.000 -name RGMII_0_rxc -waveform {0.000 4.000} [get_ports RGMII_0_rxc]
#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {gmii_clk_25m_out gmii_clk_2_5m_out}] -group [get_clocks -include_generated_clocks gmii_clk_125m_out]

set_property PACKAGE_PIN K14 [get_ports UART_1_0_txd]
set_property PACKAGE_PIN J14 [get_ports UART_1_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_0_txd]

set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_sda_io]
set_property PACKAGE_PIN U13 [get_ports IIC_1_0_sda_io]
set_property PACKAGE_PIN V16 [get_ports IIC_1_0_scl_io]

set_property PACKAGE_PIN V18 [get_ports lcd_de]
set_property PACKAGE_PIN W18 [get_ports lcd_hsync]
set_property PACKAGE_PIN W19 [get_ports lcd_vsync]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_de]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_hsync]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_vsync]

# R
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[16]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[17]}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[18]}]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[19]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[20]}]
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[21]}]
set_property -dict {PACKAGE_PIN U18  IOSTANDARD LVCMOS33} [get_ports {lcd_data[22]}]
set_property -dict {PACKAGE_PIN U19  IOSTANDARD LVCMOS33} [get_ports {lcd_data[23]}]
# G
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[8]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {lcd_data[9]}]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[10]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[11]}]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[12]}]
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[13]}]
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[14]}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[15]}]
# B
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[0]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[1]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {lcd_data[2]}]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[3]}]
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {lcd_data[4]}]
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports {lcd_data[5]}]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {lcd_data[6]}]
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {lcd_data[7]}]


set_property IOSTANDARD LVCMOS33 [get_ports {lcd_reset[0]}]
set_property PACKAGE_PIN P20 [get_ports {lcd_reset[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports lcd_clk]
set_property PACKAGE_PIN W14 [get_ports lcd_clk]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_0_tri_io[4]}]
# lcd_bl
set_property PACKAGE_PIN V17 [get_ports {GPIO_0_0_tri_io[4]}]
# lcd_tp_reset
set_property PACKAGE_PIN V13 [get_ports {GPIO_0_0_tri_io[5]}]
# lcd_tp_int
set_property PACKAGE_PIN N20 [get_ports {GPIO_0_0_tri_io[6]}]

Compile and synthesize the project, generate the bitstream, File→Export→Export hardware, and export the .xsa file.

Create a New Vitis Project

Similarly, create a new platform project and application project. The newly created code files are modified based on the 18-LVGL document and 19-AUDIO code: add new camera-related file code: create new folders emio_sccb_cfg, ov5640, and create a new file xadc.c. The final required src files are as follows:

Modify the clk_wiz file code:

xxxxxxxxxx
//clk_wiz.c
#define CLK_CFG3_OFFSET  0x20c
bool clk_wiz_cfg(uint32_t clk_device_id, double freq_MHz, double freq2_MHz)
{
    double div_factor = 0;
    uint32_t div_factor_int = 0, div_factor_frac = 0;
    uint32_t clk_divide = 0;
    uint32_t status = 0;

    // init XCLK_Wiz
    XClk_Wiz_Config *clk_cfg_ptr;
    clk_cfg_ptr = XClk_Wiz_LookupConfig(clk_device_id);
    XClk_Wiz_CfgInitialize(&clk_wiz_inst, clk_cfg_ptr, clk_cfg_ptr->BaseAddr);

    if (freq_MHz <= 0) return false;
    // config to 10X
    XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG0_OFFSET, 0x00000a01);

    // ===== config clockout1 =====
    div_factor = CLK_WIZ_IN_FREQ * 10 / freq_MHz;
    div_factor_int = (uint32_t)div_factor;
    div_factor_frac = (uint32_t)((div_factor - div_factor_int) * 1000);
    clk_divide = div_factor_int | (div_factor_frac << 8);
    XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG2_OFFSET, clk_divide);

    // ===== config clockout2 =====
    if (freq2_MHz > 0)
    {
        double div_factor2 = CLK_WIZ_IN_FREQ * 10 / freq2_MHz;
        uint32_t div_factor2_int = (uint32_t)div_factor2;
        uint32_t div_factor2_frac = (uint32_t)((div_factor2 - div_factor2_int) * 1000);
        uint32_t clk_divide2 = div_factor2_int | (div_factor2_frac << 8);
        XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG3_OFFSET, clk_divide2);
    }

    // update
    XClk_Wiz_WriteReg(clk_cfg_ptr->BaseAddr, CLK_CFG23_OFFSET, 0x00000003);

    // wait for lock
    while (1)
    {
        status = XClk_Wiz_ReadReg(clk_cfg_ptr->BaseAddr, CLK_SR_OFFSET);
        if (status & 0x00000001) // Bit0 Locked
            return true;

        usleep(1000);
    }

    return false;
}

main.c:

xxxxxxxxxx
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "xil_types.h"
#include "xil_cache.h"
#include "xparameters.h"
#include "xaxivdma.h"
#include "xaxivdma_i.h"
#include "display_ctrl_hdmi/display_ctrl_hdmi.h"
#include "vdma_api/vdma_api.h"
#include "emio_sccb_cfg/emio_sccb_cfg.h"
#include "ov5640/ov5640_init.h"

#define CAM0_VDMA_ID        XPAR_AXIVDMA_2_DEVICE_ID    // camera0 VDMA device ID
#define CAM1_VDMA_ID        XPAR_AXIVDMA_3_DEVICE_ID    // camera1 VDMA device ID
#define HDMI_VDMA_ID        XPAR_AXIVDMA_0_DEVICE_ID    // HDMI VDMA device ID
#define LCD_VDMA_ID         XPAR_AXIVDMA_1_DEVICE_ID    // LCD VDMA device ID
#define HDMI_VTC_ID         XPAR_VTC_0_DEVICE_ID        // HDMI VTC device ID
#define LCD_VTC_ID          XPAR_VTC_1_DEVICE_ID        // LCD VTC device ID
#define HDMI_CLK_WIZ_ID     XPAR_CLK_WIZ_0_DEVICE_ID    // HDMI clock wiz device ID
#define LCD_CLK_WIZ_ID      XPAR_CLK_WIZ_1_DEVICE_ID    // LCD clock wiz device ID

#define BYTES_PIXEL        3                           // RGB888 => 3bytes

//frame buffer address
unsigned int const cam0_frame_buffer_addr = (XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x1000000);
unsigned int const disp_frame_buffer_addr = cam0_frame_buffer_addr;
unsigned int cam1_frame_buffer_addr;


XAxiVdma     cam0_vdma;
XAxiVdma     cam1_vdma;
XAxiVdma     hdmi_vdma;
XAxiVdma     lcd_vdma;
DisplayCtrl  hdmi_disp_ctrl;
DisplayCtrl  lcd_disp_ctrl;
// VideoMode    *vd_mode = &VMODE_1024x600;
VideoMode    *vd_mode = &VMODE_1280x720;

int main(void)
{
    u32 status0,status1;
    u16 cmos_h_pixel; 
    u16 cmos_v_pixel; 
    u16 total_h_pixel;
    u16 total_v_pixel;

    if (vd_mode == &VMODE_800x480)
    {
        total_h_pixel = 1800;
        total_v_pixel = 600;
    }
    else if (vd_mode == &VMODE_1024x600)
    {
        total_h_pixel = 2200;
        total_v_pixel = 1000;
    }
    else if (vd_mode == &VMODE_1280x720)
    {
        total_h_pixel = 2570;
        total_v_pixel = 980;
    }

    Xil_DCacheDisable();

    cam1_frame_buffer_addr = cam0_frame_buffer_addr + vd_mode->width * BYTES_PIXEL/2;

    emio_init();
    status0 = ov5640_init(CAM0_CH0,vd_mode->width/2,
                        vd_mode->height,
                        total_h_pixel,
                        total_v_pixel);

    status1 = ov5640_init(CAM1_CH1,vd_mode->width/2,
                        vd_mode->height,
                        total_h_pixel,
                        total_v_pixel);

    if(status0 == 0 && status1 == 0)
        xil_printf("Dual OV5640 detected successful!\r\n");
    else
        xil_printf("Dual OV5640 detected failed!\r\n");

    //CAM0 VDMA
    run_vdma_frame_buffer(&cam0_vdma, CAM0_VDMA_ID, vd_mode->width, vd_mode->height,
                            cam0_frame_buffer_addr,0,0,ONLY_WRITE);
    //CAM1 VDMA
    run_vdma_frame_buffer(&cam1_vdma, CAM1_VDMA_ID, vd_mode->width, vd_mode->height,
                            cam1_frame_buffer_addr,0,0,ONLY_WRITE);

    //HDMI
    run_vdma_frame_buffer(&hdmi_vdma, HDMI_VDMA_ID, vd_mode->width, vd_mode->height,
                            disp_frame_buffer_addr,0,0,ONLY_READ);
    clk_wiz_cfg(HDMI_CLK_WIZ_ID, vd_mode->freq, vd_mode->freq2);
    DisplayInitialize(&hdmi_disp_ctrl, HDMI_VTC_ID);
    DisplaySetMode(&hdmi_disp_ctrl, vd_mode);
    DisplayStart(&hdmi_disp_ctrl);

    // //LCD
    // run_vdma_frame_buffer(&lcd_vdma, LCD_VDMA_ID, vd_mode->width, vd_mode->height,
    //                         disp_frame_buffer_addr,0,0,ONLY_READ);

    // clk_wiz_cfg(LCD_CLK_WIZ_ID, vd_mode->freq);
    // DisplayInitialize(&lcd_disp_ctrl, LCD_VTC_ID);
    // DisplaySetMode(&lcd_disp_ctrl, vd_mode);
    // DisplayStart(&lcd_disp_ctrl);

    while(1)
    {
    }
    
    return 0;
}

Compilation and Debugging

Connect the HDMI, LCD, and ZYNQ development board.

Use TYPE-C to connect the development board's JTAG port to the computer, perform Build and debug, and observe the HDMI or LCD display.